1. Field of the Invention
The present invention relates generally to a semiconductor device and a manufacturing method thereof, and more specifically, to a DRAM (Dynamic Random Access Memory) for storing and holding data signals and a manufacturing method thereof.
2. Description of the Background Art
Conventionally, a DRAM is known as a semiconductor device capable of randomly inputting information and outputting stored information. A DRAM is universally formed of a memory cell array which is a region for storing numerous pieces of information, and peripheral circuitry necessary for externally inputting/outputting signals.
FIG. 30 is a block diagram showing a conventional DRAM structure. Referring to FIG. 30, the conventional DRAM includes a memory cell array 61 for storing data signals indicative of information to be stored, an X-address buffer.decoder 62 for receiving external signals for selecting memory cells constituting a unit memory circuit and for selecting word lines, a Y-address buffer.decoder 63 for receiving external signals for selecting a memory cell and for selecting a bit line, a sense amplifier 64 for amplifying and reading out a stored signal in a memory cell, a data output buffer 65 for outputting data externally, and an R (Read)/W (Write) control circuit 66 for giving instructions as to data write/read.
Memory cell array 61 is provided with a plurality of word lines and bit lines crossing each other. Memory cells (not shown) are provided at the cross points of these word lines and bit lines. Memory cell selection is executed based on a cross point of one word line selected by X-address buffer.decoder 62 and one bit line selected by Y-address buffer-decoder 63. Data is written into the selected memory cell, or data stored in the selected memory cell is read out. Instructions as to the data write/read are given by read/write control signals (R/W) applied by R/W control circuit 66.
At the time of data writing, input data (Din) is input into a selected memory cell through R/W control circuit 66. At the time of data reading, data stored in a selected memory cell is detected by sense amplifier 64. The detected data is amplified by sense amplifier 64. The amplified data is output externally as output data (Dout) through data output buffer 65.
FIG. 31 is an equivalent circuit diagram showing a DRAM memory cell. Referring to FIG. 31, one memory cell 80 included in memory cell array 61 (see FIG. 30) includes a set of a field effect transistor 67 and a capacitor 68. The gate electrode of field effect transistor 67 is connected to a word line 69. A source/drain electrode of field effect transistor 67 on the side to be connected to capacitor 68 is connected to a bit line 70.
Description will be provided on writing/reading operations to/from memory cells. At the time of data writing, a prescribed potential is applied to word line 69, so that field effect transistor 67 is conducted and charge applied to bit line 70 is stored in capacitor 68.
At the time of data reading, a prescribed potential is applied to word line 69, so that field effect transistor 67 is conducted. The charge stored in capacitor 68 is taken out through bit line 70. The writing/reading operation to/from a memory cell is thus conducted.
FIG. 32 is a sectional view showing a structure of a conventional DRAM in section. FIG. 33 is a plan lay out showing the DRAM shown in FIG. 32.
Referring to FIGS. 32 and 33, the conventional DRAM is formed of a memory cell array 201 and a peripheral circuit 202.
Memory cell array 201 includes a p type semiconductor substrate 101, a field oxide film for element isolation 102, a p type diffusion layer for element isolation 103 formed beneath field oxide film 102, an n type source/drain diffusion layer 105 formed adjacent to field oxide film 102, an n type source/drain diffusion layer 104 formed a prescribed distance apart from an n type source/drain diffusion layer 105, a gate electrode 107 formed between n type source/drain diffusion layers 104 and 105 and on field oxide film 102 with a gate oxide film 106 therebetween, an upper insulating film 108 formed on the top of gate electrode 107, and a sidewall insulating film 109 formed on a sidewall of gate electrode 107. A pair of n type source/drain diffusion layers 104 and 105 and gate electrode 107 constitute a field effect transistor.
Memory cell array 201, further includes a storage node 110 electrically connected to n type source/drain diffusion layer 105 and formed extending over a gate electrode 107, a cell plate 112 formed on storage node 110 with a capacitor insulating film 111 therebetween. Storage node 110, capacitor insulating film 111 and cell plate 112 constitute a capacitor for storing signal charge.
Memory cell array 201 further includes an interlayer insulating film 113 formed covering the entire surface and having a contact hole 113b on n type source/drain diffusion layer 104, and a bit line 114 formed by a polycrystalline silicon layer electrically connected to n type source/drain diffusion layer 104 through contact hole 113b and formed extending over cell plate 112.
Peripheral circuit 202 includes an impurity diffusion layer 116. Bit line 114 is electrically connected to impurity diffusion layer 116 through a contact hole 113a provided in interlayer insulating film 113. Impurity diffusion layer 116 represents one end of peripheral circuit 202, and peripheral circuitry (not shown) such as a plurality of transistors are formed adjacent to impurity diffusion layers 116.
FIGS. 34 to 44 are sectional views for illustrating a manufacturing process of the DRAM shown in FIG. 32.
Referring to FIGS. 34 to 44, the manufacturing process will be described.
As shown in FIG. 34, a field oxide film for element isolation 102 is formed on a p type semiconductor substrate 101 formed of a Si substrate by means of LOCOS (Local Oxidation of Silicon). Boron (B) ions are implanted into field oxide film 102, and a p type diffusion layer for element isolation 103 is formed for reinforcing element isolation.
As shown in FIG. 35, gate oxide film (layer) 106, gate electrode (layer) 107 and upper insulating film (layer) 108 are formed. A photoresist pattern 122 is formed in a prescribed region on upper insulating film (layer) 108.
As shown in FIG. 36, gate electrode 107 and upper insulating film 108 are formed by means of anisotropic etching, using photoresist pattern 122 (see FIG. 35) as a mask. Impurity ions are implanted into p type semiconductor substrate 101, using gate electrode 107 and upper insulating film 108 as masks. N type source/drain diffusion layers 104 and 105 are thus formed. N type impurity diffusion layer 116 is formed at that time.
Referring to FIG. 37, sidewall insulating film (layer) 109 is formed on the entire surface. Then, as shown in FIG. 38 sidewall insulating film (layer) 109 (see FIG. 37) is anisotropically etched, and sidewall insulating films 109 are left on the sidewalls of gate electrode 107.
As shown in FIG. 39, storage node (layer) 110 is formed on the entire surface. A photoresist pattern 123 is formed in a prescribed region on storage node (layer) 110. Storage node (layer) 110 is anisotropically etched, using photoresist 123 as masks, and the storage node 110 is shaped into a form as shown in FIG. 40.
Then, as shown in FIG. 41, capacitor insulating film (layer) 111 and cell plate (layer) 112 are formed on the entire surface. A photoresist pattern 124 is formed in a prescribed region on cell plate (layer) 112. Cell plate (layer) 112 and capacitor insulating film (layer) 111 are selectively etched, using photoresist pattern 124 as a mask. As shown in FIG. 42, prescribed shapes of capacitor insulating film 111 and cell plate 112 are thus obtained. Storage node 110, capacitor insulating film 111 and cell plate 112 constitute a capacitor for storing signal charge.
As shown in FIG. 43, interlayer insulating film 113 is formed on the entire surface. A photoresist pattern 125 with the portions needed for contact holes opened is formed. One possible method of forming photoresist pattern 125 with the portions needed for contact holes opened will be described. First, resist is formed on the entire surface. Portions to be opened in the resist are exposed by means of reduction-type projection using a mask. Thus, photoresist pattern 125 with the portions needed for contact holes opened is obtained. After interlayer insulating film 113 is selectively etched, using photoresist pattern 125 as a mask, photoresist pattern 125 is removed. Contact holes 113a and 113b are thus formed as shown in FIG. 44. Finally, as shown in FIG. 32, polycrystalline silicon layer 114 connected electrically to n type source/diffusion layer 104 and impurity diffusion layer 116 and extending over cell plate 112 is formed. Polycrystalline silicon layer 114 constitute bit line 114.
The memory cell array 201 and peripheral circuit 202 of the conventional DRAM is formed in the above-described manner.
As in the foregoing, in the case of the conventional DRAM, memory cell array 201 and peripheral circuit 202 are formed adjacent to each other as shown in FIG. 32. Therefore, a semiconductor chip is necessary, which has an area covering memory cell array 201 and peripheral circuit 202. On the other hand, there always exist a demand for higher integration density in the field of semiconductor devices. It is not possible to sufficiently satisfy the demand by conventional methods.
Also the following problems exist in the conventional manufacturing processes. FIGS. 45 and 46 are views schematically showing the relation between the in-focus position of a lens and the cross sectional shape of resist in a lithography process. Referring to FIG. 45, resist 151 formed on a layer to be etched 150 is exposed to light in its prescribed region through a lens 152. In this case, the in-focus position 153 of lens 152 is high, and a contact hole 151a is therefore not formed to be a complete opening.
Conversely, in the state shown in FIG. 46, with the in-focus position 153 of lens 152 being low, the contact hole 151a is formed to be a complete opening. The opening diameter of the contact hole 151a increases upwardly, which makes it difficult to form the contact hole 151a as designed, resulting in a bad shape.
FIG. 47 is a view schematically showing the relation between the thickness of resist and an optimum in-focus position. Referring to FIG. 47, the optimum in-focus position for forming a contact hole 161a positioned in the A side portion is the position designated by 165a, while the optimum in-focus position for forming a contact hole 161b positioned in the B side portion is the position designated by 165b. As described above, when layer to be etched 160 has steps, the heights of the optimum positions for the A side portion and B side portion are different. When contact holes 161a and 161b are formed in the same manufacturing process, however, the heights of the in-focus positions are the same for the A side portion and B side portion.
FIGS. 48 through 50 are views each schematically showing the relation between the in-focus position of a lens and a contact hole to be formed. Referring to FIG. 48, when the in-focus positions of lenses 162a and 162b are set to be the optimum position for contact hole 161a to be formed in the A side portion, the contact hole 161a is formed just as designed in the A side portion. However, in the B side portion, the contact hole 161b to be formed does not take a shape of a complete opening, because the in-focus position 165a is too high.
Referring to FIG. 49, when the in-focus positions of lenses 162a and 162b are set to be the optimum position for contact hole 161b in the B side portion, the contact hole 161b is provided just as designed in the B side portion. However, in the A side portion, the opening diameter of the contact hole 161a increases upwardly, because the in-focus position 165b is too low. Consequently, it is not possible to provide the contact hole 161a just as designed.
Now referring to FIG. 50, when the in-focus positions of lenses 162a and 162b are set to be an intermediate position between the in-focus position shown in FIG. 48 and the in-focus position shown in FIG. 49, the contact holes 161a and 161b respectively formed in the A side portion and B side portion both take bad shapes. More specifically, the opening diameter of the contact hole 161a in the A side portion increases upwardly, while the opening diameter of the contact hole 161b in the B side portion decreases downwardly.
As in the foregoing, if layer to be etched 160 has stepped portions and thus the height of resist 161 to be formed thereon is uneven, it will be difficult to form in the same manufacturing step contact holes just as designed respectively in the positions of different heights. In such a case, if etching is conducted using the resist mask, the resultant size of layer to be etched 160 turns out to be uneven. More specifically, when resist having a contact hole larger than designed is etched, an opening formed in a layer to be etched turns out to be larger than a designed size. Conversely, if etching is conducted using resist having a contact hole smaller than designed, an opening formed in the layer to be etched becomes smaller than originally designed.
FIG. 51 is a representation schematically showing an opening portion larger than a designed size formed in a layer to be etched, and FIG. 52 is a representation schematically showing an opening portion smaller than a designed size formed in a layer to be etched. FIG. 53 is a schematic representation for illustrating a problem when an opening larger than a designed size is formed as shown in FIG. 51. Referring to FIGS. 51 and 52, assume that interconnection layers 171a and 171b are formed in a layer to be etched 170. In the state shown in FIG. 51, with the opening portion being larger than the designed size, the area of contact between layer to be etched 170 and interconnection layer 171a becomes larger. Thus, they will not be any problem such as increase of contact resistance. However, when the opening portion is larger than the designed size, as shown in FIG. 53, an overlapping margin for interconnection layer 171a formed on layer to be etched 170 becomes smaller. More specifically, when there exist a plurality of layers to be etched 170 at prescribed intervals, interconnection layer 171a to be connected to one of these etching layers 170 should be kept from electrically contacting adjacent layers to be etched 170. Therefore, as shown in FIGS. 53, tolerance b for the formation position of interconnection layer 171a having a large contact diameter is smaller than tolerance a for the formation position of interconnection layer 171c having a normal contact diameter.
Conversely, as shown in FIG. 52, if the diameter of an opening formed in a layer to be etched 170 is smaller than a designed size, the contact area between interconnection layer 171b and layer to be etched 170 becomes smaller, thus increasing contact resistance. The aspect ratio also becomes large, and the coverage characteristic deteriorates as a result.
Various problems are encountered if a contact hole is not formed as designed in size. More specifically, there exist the following problems. In other words, in the manufacturing process shown in FIG. 43, it is difficult to form photoresist pattern 125 with openings corresponding to contact holes. More specifically, interlayer insulating film 113 is not identical in height at positions under two openings of photoresist pattern 125. The depths of the two openings of photoresist pattern 125 formed thereon will be different from each other. The difference in depth between these two openings, which is larger than a focus depth in exposure, makes it difficult to form openings as designed in size. If interlayer insulating film 113 is etched using photoresist pattern 125 having such openings formed not as designed, contact holes 113a and 113b formed in interlayer insulating film 113 cannot be formed as designed in size either. It is therefore difficult to provide contact resistance between bit lines 114 formed in the contact hole and p type semiconductor substrate 101 as intended.